Salphasic Distribution of Clock Signals

نویسنده

  • Vernon L. Chi
چکیده

The design of a synchronous system having a global clock must account for the phase shifts experienced by the clock signal (clock skew) in its distribution network. As clock speeds and system diameters increase, this requirement becomes increasingly constraining on system designs. Two currently used approaches to this problem are to minimize skew by equalizing electrical path delays, and to re-cast system designs into an asynchronous (clockless) form. This paper describes a method that exploits fundamental wave propagation properties to minimize clock skews due to unequal path lengths for distribution system diameters typically up to several meters. The basic principles are developed for a loaded transmission line, then applied to an arbitrarily branching tree of such lines to implement a clock distribution network. Extension of this method to twoand three-dimensional distribution media is discussed.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Standing Wave Oscillators for Global Clock Distribution

The clock signal of modern computer processors consumes a large portion of overall chip power. By modeling global clock network wires as transmission lines and manipulating their dimensions, the global clock signal can be transformed into a standing-wave oscillator that conserves energy and reduces skew. This paper explains the lossy transmission line model and explores the effects of matching ...

متن کامل

High Speed Delay-Locked Loop for Multiple Clock Phase Generation

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

متن کامل

Clock Distribution in Synchronous Systems

In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Because this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the networks used in their distribution. Clock signals are often regarded as simple control signals; however, thes...

متن کامل

Clock Distribution in RNS-based VLSI Systems

Clock distribution networks synchronize the flow of data in digital systems, and the features of the clock signal affect system performance and reliability. The great advances in integration levels and speed requirements in actual digital systems lead to enormous complexity in synchronization. Differences in delay of clock signals along clock paths, due to different lengths or active elements s...

متن کامل

Design of a High Speed Clock Distribution Network

In this note the analog effects that prevent integrity of digital signals are discussed with reference to the implementation of a reliable distribution network for a 60 MHz clock onto a card with a 64-bit data bus.

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2010